This invention relates to programmable logic device integrated circuits, and more particularly to phase-locked loop (xe2x80x9cPLLxe2x80x9d) or delay-locked loop (xe2x80x9cDLLxe2x80x9d) circuitry usable in the clock signal distribution networks of programmable logic device integrated circuits.
It is known to include PLL or DLL circuitry on programmable logic devices to help counteract xe2x80x9cskewxe2x80x9d and excessive delay in clock signals propagating on the device (see, for example, Jefferson U.S. Pat. No. 5,699,020 and Reddy et al. U.S. Pat. No. 5,847,617, both of which are hereby incorporated by reference herein in their entireties). For example, PLL or DLL circuitry may be used to produce a clock signal which is advanced in time relative to a clock signal applied to the programmable logic device. The advanced clock signal is propagated to portions of the device that are relatively distant from the applied clock signal so that the propagation delay of the advanced clock signal brings it back into synchronism with the applied clock signal when it reaches the distant portions of the device. In this way all portions of the device receive synchronous clock signals and clock signal xe2x80x9cskewxe2x80x9d (different amounts of delay in different portions of the device) is reduced.
It is now conventional to include in PLL or DLL circuitry on a programmable logic device xe2x80x9clumpedxe2x80x9d circuit components that are intended to equal the distributed propagation delay experienced by the clock signal being modified by the PLL or DLL circuitry. However, it can be difficult to accurately emulate distributed propagation delay with lumped or discrete circuit elements. The lumped circuit elements are usually disposed on the device in a relatively localized area. The clock network, on the other hand, extends throughout the device and therefore operates in a different electrical environment (e.g., due to coupling to and from adjacent circuit elements, loading, etc.) than is experienced by the lumped circuitry. Phenomena such as fabrication process variations, temperature changes, and power supply voltage differences can affect lumped circuit components and distributed circuit performance differently, making it difficult to accurately match distributed propagation delay with lumped circuit components. Scaling a circuit up or down (e.g., for fabrication using different technologies or to provide a family of products of different sizes (i.e., with different amounts of programmable logic)) may also have different effects on lumped and distributed circuit components, and therefore reduce the desired accuracy of the PLL or DLL circuitry or necessitate a redesign of that circuitry.
In view of the foregoing it is an object of this invention to provide improved PLL and DLL circuitry for programmable logic devices.
It is a more particular object of this invention to provide PLL and DLL circuitry for programmable logic devices that more accurately emulates the distributed propagation delay of the clock signal being manipulated by the PLL or DLL circuitry.
These and other objects of the invention are accomplished in accordance with the principles of the invention by providing PLL or DLL circuitry on a programmable logic device in which the feedback loop of the PLL or DLL is constructed to substantially parallel and duplicate at least a portion of the clock signal distribution network that receives the clock signal manipulated by the PLL or DLL. In this way the feedback loop of the PLL or DLL is subject to substantially the same distributed propagation delay effects as the clock signal distribution network receiving the clock signal modified by the PLL or DLL. This increases the accuracy with which the PLL or DLL circuitry emulates delay in the clock signal distribution network. Moreover, emulation accuracy is maintained despite variations due to fabrication process, temperature, power supply voltage, and even changes in circuit scale.
The signal propagating in the above-described distributed feedback loop of the PLL or DLL circuitry may be slightly shifted in time (preferably by a programmably selectable amount) relative to the signal in the clock signal distribution network. In this way one PLL or DLL can provide two different clock signals, each of which has an accurate phase relationship to an input clock signal applied to the programmable logic device. One of these signals can be used to clock input, output, or input/output (generically xe2x80x9cI/Oxe2x80x9d) registers of the programmable logic device. The other of these signals can be used as an output clock signal of the programmable logic device.
Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description of the preferred embodiments.